1. Field of the Invention
The invention relates generally to memory systems and methods of handling memory system commands.
2. Description of Related Art
The concept of a “memory system” now encompasses a great variety of circuits and related control methods enabling the transfer, storage and retrieval of digital data. Once memory systems were associated with only computers systems and similar computational logic platforms. Now, a great host of consumer products ranging from cell phones to automobiles to refrigerators include memory systems of varying complexity.
A generic memory system is conceptually illustrated in Figure (FIG.) 1, wherein a memory 2 is provided to store data received from a memory controller 1 via a channel 3.
The memory 2 may be volatile or nonvolatile in its operating nature. A volatile memory retains stored data only so long as power is applied to the memory. Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) are well known categories of volatile memories. In contrast, nonvolatile memories have the ability to retain stored data in the absence of applied power. Flash memory is one popular example of a nonvolatile memory.
Regardless of memory type and related storage capabilities, a memory must typically be associated with some kind of memory controller. Memory controller 1 shown in FIG. 1 may take many different forms including a generic processor or controller, a direct memory address (DMA) controller, a host device central processor unit (CPU), a dedicated data switch or transfer element, etc. In all of its varied forms, and regardless of additional functionality, memory controller 1, at its basic relevant functionality, controls the transfer of data to and/or from memory 2.
Data transfer between memory controller 1 and memory 2 is accomplished via a channel 3. Channel 3 may be hardwired or wireless in its implementation. For example, data may be wirelessly transferred between memory controller 1 and memory 2 via radio frequency (RF) channel(s), infrared channel(s) and/or magneto-electric channel(s). More typically, memory controller 1 and memory 2 are connected via a hardwired channel formed by one or more buses and/or various signal lines. In this context, a “bus” is merely a collection (physical or operational) of signal lines commonly operated in relation to a block of data and/or a timing segment.
The examples shown in FIG. 2 are but several of the numerous types of hardwire channels 3 that might be used to connect memory 2 with a memory controller 1. In the first illustrated example, memory 2 and memory controller 1 are connected by a plurality of unidirectional control signal lines (C/S), a unidirectional address bus (ADDR), and a bidirectional data bus (DQ). Assuming for purposes of illustration that memory 2 is a DRAM, the control signal lines may be used to communicate commonly used control signals such as chip select (CS), row address strobe (RAS), column address strobe (CAS), write enable (WE), etc. In this configuration, the address bus may be used to communicate multiple address bits identifying unique location(s) in memory 2 to which, or from which data is to be read or written, respectively. Data written to memory 2 will hereafter be referred to a “write data” and data retrieved from memory 2 will be referred to as “read data.”
In the second illustrated example of FIG. 2, the unidirectional collection of control signal lines and the address bus are effectively combined into a single control/address (C/A) bus. This bus configuration is commonly associated with memory systems using packetized commands. That is, certain memory system architectures utilize the flexibility and efficiency offered by configuring data into so-called “data packets.” The definition and use of data packets are well understood by those skilled in the art and are the subject of many conventional protocols and standards.
In the third illustrated example of FIG. 2, a common unidirectional C/A bus structure is also used to communicate write data from memory controller 1 to memory 2. Here again, the write data may be grouped into one or more data packet(s) along with related control data and/or address data.
Finally, in the fourth illustrated example of FIG. 2, a common bidirectional bus is used to communicate not only control data, address data and write data from memory controller 2 to memory 1, but also read data from memory 2 to memory controller 1. Only certain control signal lines are otherwise defined between memory controller 1 and memory 2 outside the common bidirectional bus. In this example, the read data may be packetized before being communicated from memory 2 to memory controller 1.
One notable characteristic of conventional and emerging memory systems is an increasing demand for greater data bandwidth (i.e., available data per unit operation) and/or data throughput (available data per period of time). Data bandwidth may be increased by increasing the number of data bits being communicated to/from a memory in a memory system operation. Data throughput may be increased by the number of data bits being communicated to/from a memory in a memory system operation and/or increasing the speed with which each memory system operation is performed.
Given concurrent commercial motivations to reduce memory system size and power consumption while maximizing available data bandwidth and data throughput, it is not surprising that certain practical limitations have quickly arisen. For example, the number of signal lines connecting a memory controller with memory may be limited by the size of the memory or memory controller and/or the corresponding number of available connection (input/output) pads. Given such physical limitations, all or some signal lines in a memory system may be multiplexed in their use.
Regardless of the physical connections between a memory and memory controller, almost all contemporary memory systems are being run at increasingly fast clock speeds. Increasingly fast clock speeds facilitate greater data throughput. Enhanced data throughput is highly desirable for many commercial applications.
Unfortunately, increasingly fast clock speeds also increase the likelihood of data communication (transmission and/or reception) errors. Indeed, memory systems have become so complex and data transfer speeds have become so fast, that many contemporary memory systems now incorporate error detection and/or error correction (singularly or collectively indicated as “EDC”) capabilities to mitigate the inevitable consequences of data errors.
EDC capabilities were once used primarily for long-haul (or bulk) data traffic such as telephone networks and satellite communication systems. Now, however, the advantages of incorporating EDC capabilities within a memory system are well appreciated. There are many different types of EDC protocols, techniques, schemes, and related circuits and software. One class of relatively simple error detection techniques are conventionally used to implement a functionality referred to as a cyclic redundancy checker (CRC). More sophisticated EDC techniques are capable of not only detecting the presence of one or more error(s) in communicated data, but also of correcting the detected error(s).
Nearly all EDC techniques are implemented by adding additional (“overhead”) data bits to a block of data being communicated. That is, the data block is first run through a mathematical or logical calculation in order to produce corresponding EDC data. The EDC data is then transferred along with the data block. At the receiving end, the data block is again run through a similar mathematical/logical calculation and the resulting data compared to the received EDC data. A successful comparison indicates an error free block of data. A failed comparison indicates one or more errors in the data block. When more sophisticated EDC techniques are used, these error(s) may be corrected by further resort to the overhead data.
As the operating speed and overall complexity of memory systems has increased, the control data, address data, write data, read data, etc., communicated between a memory controller and a memory has become increasingly susceptible to errors. The potentially catastrophic effects of such errors is clear. Errant control data, address data and/or write data is particularly threatening since such data is capable of corrupting the data stored in memory.
As a result of the foregoing, many contemporary memory controllers now include specialized circuits and/or software routines capable of generating EDC data in relation to memory system operations (e.g., read/write operations). A memory connected to the memory controller incorporating EDC capabilities (e.g., hardware and/or software) must be functionally capable of segregating EDC data from other data, and thereafter using the EDC data to verify the integrity of some portion of the other data.
Additionally, the memory often includes specialized circuits and/or software routines capable of notifying the memory controller when errant data has been identified. In response to a notification from the memory, the memory controller may re-send the errant data.
Where the EDC data provided by the memory controller is enabling, the memory may additionally or alternately include error correction circuits and/or software routines capable of correcting identified error(s) in the received data. The overall power and sophistication of a memory system's EDC capabilities is a matter of design choice, but increasing some provision of EDC capabilities is being made in contemporary memory systems.
EDC capabilities are particularly beneficial in the context of memory systems using data packet communication techniques. That is, individual data packets may be defined to include corresponding EDC data along with other types of data (e.g., control data, address data, write data, etc.). The EDC data may be associated with (e.g., derived from and used to detect and/or correct errors in) any one or more of these other data types.
While EDC capabilities offer great benefits in the verification of data being communicated between a memory controller and a memory, such capabilities come at a price. The greatest price is typically imposed on the overall speed of memory system operation. EDC operations run in the memory controller, and more particularly, EDC operations run in the memory generate a data throughput bottleneck within memory systems. Thus, the contemporary memory system designer faces the competing demands of increasing data throughput, which requires the streamlining, simplifying, and expediting of memory system operations, and assuring data integrity, which requires sophisticated and relatively slow EDC operations.